This application claims priority to Korean Patent Application 2002-0041975, filed on Jul. 18, 2002, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to integrated circuit memory devices, and in particular to read only memory (ROM) devices having virtual ground and bit lines.
A ROM integrated circuit device includes a ROM storage cell block including storage cells. Bits lines from the storage cells are used to output data from the storage cells during a read operations. Such devices may also include virtual ground lines that may be positioned adjacent the bit lines on the integrated circuit device. As integration density of the devices increases, the widths and lengths of lines formed in the integrated circuit device generally are reduced. As a result, electrical coupling may result between adjacent ones of the virtual ground lines and bit lines.
A variety of approaches may be taken to reduce or prevent such an electrical coupling from adversely affecting performance of the device. For example, when the virtual ground lines and the bit lines are in a precharged state, the supply of the precharge voltage to the bit lines may be stopped when the virtual ground lines are being discharged to ground. As a result, the voltage of the bit lines may be affected by the virtual ground lines and drop to a predetermined level lower than the precharge voltage. To compensate for this drop, the supply of the precharge voltage to the bit lines is not stopped until a predetermined period of time after the virtual ground lines are grounded. Thus, the affect of the virtual ground lines on the bit lines may be reduced or eliminated.
However, because the virtual ground lines and the bit lines are conventionally precharged at the same time, as described above, the precharge voltage is still applied for a predetermined period of time after the virtual ground lines are grounded. Thus, a short-circuit current may flow through the virtual ground lines and, as a result, the virtual ground lines may not be at a ground voltage level. This state may continue until the supply of the precharge voltage to the virtual ground lines stops. If the virtual ground lines are not fully grounded, the operational speed of the ROM integrated circuit device may decrease and its power consumption may increase.
Embodiments of the present invention include read only memory (ROM) integrated circuit devices including one or more storage cells. A virtual ground line and a bit line are coupled to the storage cell. A precharge circuit independently controls timing of precharging of the virtual ground line and the bit line. More particularly, the precharge circuit may be configured to deactivate precharging of the virtual ground line before deactivating precharging of the bit line.
In further embodiments of the present invention, the precharge circuit includes a virtual ground line precharge circuit that activates precharging of the virtual ground line responsive to a virtual ground line precharge signal and a bit line precharge circuit that activates precharging of the bit line responsive to a bit line precharge signal. The bit line precharge signal is deactivated after deactivation of the virtual ground line precharge signal.
In other embodiments of the present invention, a virtual ground line discharge circuit is coupled to the virtual ground line. The virtual ground line precharge circuit deactivates precharging of the virtual ground line substantially concurrently with activation of the virtual ground line discharge circuit. The virtual ground line discharge circuit may couple the virtual ground line to ground and the virtual ground line precharge circuit may couple the virtual ground line to a precharge voltage. The bit line precharge signal may couple the bit line to the precharge voltage. The virtual ground line discharge circuit may activate discharging of the virtual ground line responsive to a discharge control signal.
In further embodiments of the present invention, the virtual ground line precharge circuit is configured to activate precharging of the virtual ground line responsive to an address control signal and the virtual ground line discharge circuit is configured to activate discharging of the virtual ground line responsive to an address signal associated with the storage cell. The virtual ground line precharge circuit may include a virtual ground line precharge controller and a virtual ground line precharging unit. The virtual ground line precharge controller is configured to generate a virtual ground line precharge enable signal responsive to the address control signal and the virtual ground line precharge signal. The virtual ground line precharging unit includes a transistor having the virtual ground line precharge enable signal coupled to a gate thereof.
In other embodiments of the present invention, the virtual ground line precharge controller is configured to generate the virtual ground line precharge enable signal as a Boolean NAND operation having the address control signal and the virtual ground line precharge signal as inputs. The bit line precharge circuit may include a bit line precharge controller and a bit line precharging unit. The bit line precharge controller is configured to generate a bit line precharge enable signal responsive to the bit line precharge signal. The bit line precharging unit includes a transistor having the bit line precharge enable signal coupled to a gate thereof.
In further embodiments of the present invention, the virtual ground line discharge circuit includes a discharge controller that generates a discharge signal responsive to the discharge control signal and the address signal associated with the storage cell and a transistor having the discharge signal coupled to a gate thereof. The discharge controller may be configured to generate the discharge signal as a Boolean NAND operation having the discharge control signal and the address signal associated with the storage cell as inputs. The integrated circuit device may include a plurality of storage cells, each of the plurality of storage cells having an associated bit line and virtual ground line, precharging of the associated bit line and virtual ground line of each storage cell being independently controlled by the precharge circuit.
In other embodiments of the present invention, methods are provided of controlling precharging of a read only memory (ROM) integrated circuit device including a storage cell and a virtual ground line and a bit line coupled to the storage cell. The methods include independently controlling timing of precharging of the virtual ground line and the bit line. Independently controlling timing of precharging may include deactivating precharging of the virtual ground line before deactivating precharging of the bit line. The methods may also include discharging the virtual ground line substantially concurrently with deactivating precharging of the virtual ground line.
According to further embodiments of the present invention, a ROM integrated circuit device is provided including a ROM cell block, a virtual ground line, a virtual ground line precharging unit, a switch, a bit line, and a bit line precharging unit. The ROM cell block stores data. The virtual ground line is connected to the ROM cell block. The virtual ground line precharging unit precharges the virtual ground line in response to a virtual ground line precharge signal. The switch is connected to the virtual ground line and grounds the virtual ground line in response to a discharge signal. The bit line is connected to the ROM cell block. The bit line precharging unit precharges the bit line in response to a bit line precharge signal.
In some embodiments of the present invention, the ROM integrated circuit device further includes a virtual ground line precharge controller that receives a virtual ground line precharge control signal and an address control signal and outputs the virtual ground line precharge signal. Here, if the virtual ground line precharge control signal and the address control signal are at a logic xe2x80x9chighxe2x80x9d level, the virtual ground line precharge signal is at a logic xe2x80x9clowxe2x80x9d level and if at least one of the virtual ground line precharge control signal and the address control signal is at a logic xe2x80x9clowxe2x80x9d level, the virtual ground line precharge signal is at a logic xe2x80x9chighxe2x80x9d level.
In other embodiments of the present invention, if the virtual ground precharge signal is at a logic xe2x80x9clowxe2x80x9d level, the virtual ground line precharging unit is activated to precharge the virtual ground line and if the virtual ground line precharge signal is at a logic xe2x80x9chighxe2x80x9d level, the virtual ground line precharging unit is deactivated (inactivated). The ROM integrated circuit device may further include a bit line precharge controller that receives a bit line precharge control signal and outputs the bit line precharge signal. In such embodiments, if the bit line precharge control signal is at a logic xe2x80x9chighxe2x80x9d level, the bit line precharge signal is at a logic xe2x80x9clowxe2x80x9d level and if the bit line precharge control signal is at a logic xe2x80x9clowxe2x80x9d level the bit line precharge signal is at alogic xe2x80x9chighxe2x80x9d level.
In further embodiments of the present invention, if the bit line precharge signal is at a logic xe2x80x9clowxe2x80x9d level the bit line precharging unit is activated to precharge the bit line and if the bit line precharge signal is at a logic xe2x80x9chighxe2x80x9d level the bit line precharging unit is deactivated (inactivated). The ROM integrated circuit device may further include a discharge controller that receives a discharge control signal and an address signal and outputs the discharge signal. In such embodiments, if at least one of the discharge control signal and the address signal is at a logic xe2x80x9clowxe2x80x9d level, the discharge signal is at a logic xe2x80x9chighxe2x80x9d level and if the discharge control signal and the address signal are at a logic xe2x80x9chighxe2x80x9d level, the discharge signal is at a logic xe2x80x9clowxe2x80x9d level. If the discharge signal is at a logic xe2x80x9chighxe2x80x9d level, the switch may be activated to ground the virtual ground line and, if the discharge signal is at a logic xe2x80x9clowxe2x80x9d level, the switch may be deactivated.
In further embodiments of the present invention, a ROM integrated circuit device includes a ROM cell block, a plurality of virtual ground lines, a plurality of virtual ground line precharging units, a plurality of switches, a plurality of bit lines, and a plurality of bit line precharging units. The ROM cell block stores data. The plurality of virtual ground lines are connected to the ROM cell block. The plurality of virtual ground line precharging units precharge the plurality of virtual ground lines in response to a virtual ground line precharge signal. The plurality of switches are connected to one of the plurality of virtual ground lines and ground the virtual ground lines in response to a discharge signal. The plurality of bit lines are connected to the ROM cell block. The plurality of bit line precharging units precharge the plurality of bit lines in response to a bit line precharge signal.